1. Field of the Invention
The present invention relates to a resolver signal processing system that executes processing such as, for example, to measure the angle of rotation of a rotator, based on the resolver output signals.
2. Description of the Related Art
Resolvers are known that detect an angle of rotation of a rotator""s rotor. The measured results are typically used for servo control of the rotator.
FIG. 1 shows a functional block diagram that schematizes a predecessor servo control system using the resolver, implemented by prior art. The resolver 2 outputs signals produced by modulating the amplitude of reference signal supplied from a sine-wave oscillator 4, dependent on the angle of rotor rotation. The resolver 2 and a motor 6 are configured to share a same shaft on which they both rotate, so that the angle of rotation of the rotor of the motor 6 can be detected based on the resolver output signals.
The measurement of an angle of rotation is conventionally performed using a circuit commonly called a-resolver/digital (R/D) converter. To the primary winding of the resolver, a reference signal, sine wave E1xc2x7sin xcfx89t (E1 represents the amplitude of the reference signal) is input. The outputs are Vsin and Vcos voltages that are produced at the ends of two secondary windings positioned apart from each other by 90 degrees of phase difference. The Vsin and Vcos resolver output signals are respectively equal to modulated signals E2xc2x7sin (xcfx89t+xcex1) sin xcex8 and E2xc2x7sin (xcfx89t+xcex1) cos xcex8 which are produced by modulating the reference signal, depending on the angle of rotor rotation xcex8. (E2 is the amplitude of the modulated signals, xcex1 is the phase shift of the modulated signals from the reference signal, and E2/E1 is the ratio of transformer for the modulated signals to the reference signal.) After amplified by differential amplifiers 8 and 10 respectively, these signals are input to an R/D converter 12 and an analog-digital (A/D) converter 14. The R/D converter 12 carries out a Phase Locked Loop (PLL) control process in the following manner: The R/D converter 12 calculates a value of sin (xcex8xe2x88x92xcfx86) from sin xcfx86 and cos xcfx86 signals relative to the reference angle of rotation xcfx86, which are, for example, controlled by a voltage control oscillator, and the Vsin and Vcos resolver output signals including the angle of rotor rotation xcex8; and increments or decrements a value of count corresponding to xcfx86 so that the phase difference (xcex8xe2x88x92xcfx86) will be 0. Thus, the R/D converter 12 detects and outputs a value of xcfx86 as the value of the angle of rotor rotation xcex8 when the PLL control is convergent, that is (xcex8xe2x88x92xcfx86)=0.
A central processing unit (CPU) 16, operating according to the clock, to which the angle of rotation xcex8 and other data are input from the R/D converter 12 and the result of conversion and associated data are input from the A/D converter 14, executes the processing for servo control of the motor 6 and fault detection for the resolver 2. For example, the CPU 16 generates PWM pulses to drive the motor 6, based on the clock. Current values of IU and IV corresponding to two phases of a three-phase signal for driving the motor 6 are converted into digital values through the A/D converter 14 and fed back to a control loop processing section 22 of the CPU. Using the result of feedback, the control loop processing section 22 executes servo control loop processing to set the voltages in the U, V, and W phases which are output as PWM voltage requirements.
For fault detection, for example, at a point where the amplitude of the Vsin and Vcos resolver output signals reaches the maximum, the CPU 16 calculates the square sum of these signals (Vsin2+Vcos2) The phase difference between the peak amplitude point of the Vsin and Vcos resolver output signals and the peak amplitude point of the reference signal is constant. An interrupt signal generator section for resolver amplitude check 24 detects the timing of the peak amplitude of the resolver output signals, based on the result of detection of the peak amplitude of the reference signal output from the sine-wave oscillator 4. When a faulty timing is detected, the interrupt signal generator section 24 issues a signal for interrupting the servo control loop executed by the control loop processing section 22 within the CPU 16, causing the CPU 16 to halt the servo control loop and execute the processing for fault detection.
FIG. 2 shows a flowchart for outlining the conventionally applied servo control processing. When the servo control processing starts, the A/D converter is activated (step S50) to execute the A/D conversion of, for example, IU and IV. The control loop processing section 22 obtains the resolver data which has been output from the R/D converter 12 (step S55) and computes an electrical angle xcex8e (step S60), while receiving the A/D converted IU and IV data (step S65). In order to facilitate the control of the motor, coordinate transformation is performed. Thus, the IU and IV data are transformed into magnetized current Id and torque current Iq, respectively (step S70). The control loop processing section 22 Computes a d-axis voltage requirement and a q-axis voltage requirement, based on the values of Id and Iq (steps 375 and S80). The voltage requirements for d and q axes thus calculated are transformed into three phase coordinates of U, V, and W phases (step S85) Based on the result of this transformation, PWM voltage requirements are generated (step 90). According to the PWM voltage requirements, a triangular wave comparator section 26 generates PWM pulses to drive a driver 28, and the correspondingly generated IU, IV, and IW currents are supplied to the motor 6.
FIG. 3 shows a flowchart outlining example conventionally applied resolver fault/normal judgment processing. The interrupt signal generator section for resolver amplitude check 24 consists of a comparator that holds a preset threshold for the reference signal peak level and generates an interrupt signal at a timing when the reference signal value exceeds the threshold. In synchronization of this interrupt signal, the fault/normal judgment processing is activated. The A/D converter 14 is then activated (step S100) and the Vsin and Vcos resolver output signals are acquired by the control loop processing section 22 (step S105) . The acquired signals nearly correspond to the peak point of the reference signal (sin xcfx89t=xc2x11) and their values are xc2x1E2xc2x7sin xcex8 and xc2x1E2xc2x7cos xcex8, respectively. Hence, principally, the square sum (Vsin2+Vcos2) must become E2. The square sumof these signals is calculated (stepS110) According to whether the resultant square sum exceeds the threshold which has typically been set near E2, the fault/normal judgment is carried out. If the judgment indicates a fault, fault corrective action is executed (S120).
In the conventional implementation of such system, the resolver output signals are sampled for fault/normal judgment, based on the reference signal generated by the sine-wave oscillator 4, whereas the servo control processing for the motor is carried out in synchronization with the output from the CPU""s time base section 20 and this output is based on the clock. In this way, the fault/normal judgment and the servo control are based on different signals which are supplied independently; i.e., the output from the sine-wave oscillator 4 and the clock. Consequently, the resolver output signal sampling timing is asynchronous with the servo control cycle and an interrupt for this sampling may occur during the control loop. Unless the resolver output signal sampling is carried out on a real-time basis in synchronization with the peak point of the reference signal, the accuracy of fault detection decreases. For this reason, the computation for servo control loop must pause whenever the interrupt for resolver output signal sampling occurs. This is a drawback, as the output of the voltage requirements is delayed, causing variation in the response ability of the motor control.
Because interruption of the CPU 16 processes is software controlled, the time from the interrupt occurring until the CPU has been instructed to sample the resolver output signals depends on the software response time, which in turn varies with the specific software employed. In some cases, this time may be too short or long and consequently sampling may occur off the maximum amplitude point of the resolver output signals. This is also a problem, inducing the risk of decreasing the accuracy of fault detection. Another problem inducing the same risk is also posed when the phase in which the amplitude of signals from the resolver 2 reaches the peak is shifted due to its temperature characteristics.
Predecessor resolver signal processing systems require the R/D converter to detect an angle of rotation. Because this R/D converter is relatively expensive and its circuit size is large, there is also a drawback that these systems are expensive and relatively large.
In order to obtain the resolver positional data in synchronization with the serve control cycle, some arrangement is required so that the outputs from the R/D converter will be read at certain intervals. To accomplish this, an additional circuit is required for the R/D converter to interface with a bus of the CPU 16. This creates further problems with increased cost and size of the system.
The object of the present invention is to provide a lower cost resolver signal processing system with simple structure and capable of executing highly-accurate fault detection and servo control, thereby addressing the drawbacks and problems described above.
A resolver signal processing system offered by the invention comprises reference signal generating means for generating reference signal that cycles in a given period on the basis of a clock; sampling trigger signal generating means to generate a sampling trigger signal, which cycles in a given period on the basis of the period of said reference signal, in synchronization with the clock; detection means to sample the output signals from the resolver in response to the sampling trigger signal and detect sine and cosine modulated signals in accordance with the angle of rotation from the resolver output signals; and angle of rotation determining means to determine the angle of rotation, based on the sine and cosine modulated signals.
This invention allows both reference signal and sampling trigger signal to be generated based on the same clock. The generation timing relation between both signals, once set, is maintained afterward; that is, the synchronization of reference signal with sampling trigger signal is assured. Owing to the fact that resolver output signals are produced by modulating the amplitude of the reference signal and the above synchronization between the two signals is maintained, once the sampling of these signals has been set to take place at signal amplitude peak point, these signals are always sampled at that point and basically without being affected by clock variation. Thus, the detection of sine and cosine modulated signals is carried out with accuracy and the angle of rotation is determined by using these modulated signals.
A resolver signal processing system offered by the invention also comprises rotator control trigger signal generating means for generating a rotator control trigger signal in synchronization with the above sampling trigger signal, based on the clock; and rotator control means to start the control of the rotator in response to the rotator control trigger signal.
One of the features of this invention is that the processing for controlling the rotator is synchronous with the resolver output signal sampling, based on the same clock. The sampling can be set to take place at a predetermined timing relative to the rotator control processing. For example, arrangement can be made so that the rotator control processing always starts after the completion of the sampling. This prevents the rotator control processing from pausing whenever the interrupt for sampling occurs.
The sampling trigger signal generating means of the resolver signal processing system will generate sampling trigger signals at timings that discretely correspond to two peaks of the reference signal amplitude, positive and negative during one cycle period of the reference signal.
In addition to the improved accuracy of determining the angle of rotation at sampling points, owing to the fact that the sampling timings are set synchronous with resolver output signals as described above, sampling is performed two times during one period of the reference signal. This feature of the invention improves the resolution of the angle of rotation by shortening the sampling cycle for measuring the angle of rotation.
The sampling trigger signal generating means of the resolver signal processing system will also continuously generate a plurality of sampling trigger signals over a given peak seeking period; detect the peak points of the reference signal, based on the values of the resolver output signals sampled in response to the continuously generated sampling trigger signals; and determine the timings of generating the sampling trigger signals after the peak seeking period, based on the reference signal peak points thus detected as above.
Fundamentally, the sampling of resolver output signals is aimed at their amplitude peaks and the signals are thus sampled near either positive or negative peaks, or near both peaks. The system offered by the invention temporarily samples resolver output signals in a short cyclic period to detect their peak points. The peak points are points at which the absolute amplitude of the sampled signals becomes maximum. Once the peak points have been detected, subsequent sampling is performed at timings corresponding to these points. The resolver output signal and the reference signal are synchronous with each other, but the peak points of both signals do not always match. There is a possibility of one peak point of one signal being shifted from the corresponding peak point of the other signal by a certain segment of phase. If this shift distance is unknown, sampling according to the invention can be executed in a burst manner to determine the shift distance. For example, the burst sampling may be performed in the initial stage of system start.
Furthermore, the sampling trigger signal generating means of the resolver signal processing system generates a pair of sampling trigger signals such that the second one takes place after a fixed interval from the first one occurring; detects a point of peak amplitude of the reference signal relative to the timings of the above pair of sampling trigger signals, based on the values of the resolver output signals sampled in response to the pair of sampling trigger signals; and determines the timings of generating the next, pair of sampling trigger signals, based on the relative peak point of the reference signal thus detected as above.
In another aspect of this invention, a pair of resolver output signals are sampled such that the second one takes place after a fixed interval from the first one. Based on the comparison between the values of the two sampled signals, the resolver output signal amplitude peak is deduced to take place before, between, or after the timings of sampling these signals. The result of this deduction is fed back to the process of determining the next sampling timings. As an example, let us consider the case where a pair of resolver output signals is sampled at certain timings with regard to the positive peak at which the resolver output signal amplitude becomes maximum. If the value of the preceding one is smaller than the succeeding one, the peak is deduced to take place between and after the timings of sampling the two signals. Then, the timings for sampling the next pair are delayed by the required number of clocks. As a result, if the values of newly sampled pair become almost the same, the sampling timing shift is stopped with the estimated peak being between the sampling timings. If the value of the preceding one is still smaller than the succeeding one, the timings for further sampling are shifted more in the same direction. Inversely, if the value of the preceding one is larger than the succeeding one, the sampling timings are shifted in the reverse direction. By executing this operation at certain intervals or all times, the system achieves the minute adjustment of sampling timings so that sampling will occur, matching the peak point.
The angle of rotation determining means of the resolver signal processing system comprises a table of angles of rotation for associating angles of rotation with possible sets of a value of sine function and a value of cosine function; and angle of rotation reading means to obtain a unique angle of rotation from this table, based on the value derived from the sine and cosine modulated signals.
In the following, the relationship between sine and cosine functions and their arguments of angle of rotation are discussed. There are two angles of rotation, giving a value of sine function. Similarly, there are two angles of rotation, giving avalue of cosine function. Thus, only a single value of sine function or cosine function cannot determine a unique angle of rotation. A set of a sine function value and a cosine function value must, however, correspond to one angle of rotation. This invention provides a table of angles of rotation that associates angles of rotation with possible sets of values of sine function and of cosine function. This table can be defined as a two-dimensional table in which a value of angle is specified by a set of a sine function parameter and a cosine function parameter.
In another aspect of the present invention, the above-mentioned angle of rotation determining means comprises a table of angles of rotation for associating angles of rotation with possible values of tangent function; and angle of rotation reading means to obtain a unique angle of rotation from this table, based on the value derived from the sine and cosine modulated signals.
A tangent function with an argument of angle of rotation can have the same value twice for one full rotation because it changes by a period of xcfx80. This invention ensures that the determination of a quadrant in which the angle of rotation is positioned is made, based on the plus or minus sign of the obtained values of sine and cosine functions. The invention also provides a one-dimensional table of angles of rotation that holds possible values of tangent function associated with angles of rotation. By using a tangent function as a parameter, an angle within one rotation can be fixed. A value of tangent function is obtained, based on the values of sine and cosine functions. According to the obtained value of tangent function within a quadrant determined as described above, the table is searched and a unique angle of rotation is determined. One method of obtaining a value of tangent function from the values of sine and cosine functions is a division algorithm, but not limited to it. The use of a value of cotangent function instead of a value of tangent function does not conflict with the nature of the invention.
The resolver signal processing system includes fault detection means for detecting a fault in the resolver, based on the comparison between the square sum of the sine and cosine modulated signals and the amplitude of these modulated signals.
Mathematically, the square sum of a value of sine function and a value of cosine function corresponding to any given angle of rotation is 1. The system according to the invention can sample resolver output signals at their peak amplitude with stable accuracy by making the sampling timings synchronous with the resolver output signal peaks as described above. Thus, the above square sum derived from the sampled signals remains constant with accuracy during normal operation of the resolver. As a result, precise fault detection is accomplished, based on the variation from the constant value of square sum.